cystech electronics corp. spec. no. : c403n3 issued date : 2006.05.22 revised date :2011.12.13 page no. : 1/7 MTNK2N3 cystek product specification n-channel mosfet MTNK2N3 description the MTNK2N3 is a n-channel enhancement-mode mosfet. features ? low on-resistance ? high esd ? high speed switching ? low-voltage drive(4v) ? easily designed drive circuits ? easy to use in parallel ? pb-free package symbol outline MTNK2N3 sot-23 g s g gate s source d drain g s d d ordering information device package shipping marking MTNK2N3 sot-23 (pb-free) 3000 pcs / tape & reel 702
cystech electronics corp. spec. no. : c403n3 issued date : 2006.05.22 revised date :2011.12.13 page no. : 2/7 MTNK2N3 cystek product specification absolute maximum ratings (ta=25 c) parameter symbol limits unit drain-source voltage v dss 60 v gate-source voltage v gss 20 v t a =25 c@v gs =10v 640 ma continuous drain current t a =70 c@v gs =10v i d 500 ma pulsed drain current *1, 2 i dm 950 *1 ma total power dissipation p d 1.38 *2 w linear derating factor 0.01 w/ c thermal resistance, junction to ambient rth,j-a 90 *2 c/w esd susceptibility 1000 *3 v operating junction temperature range t j -55~+150 c storage temperature range tstg -55~+150 c note : *1. pulse width 300 s, duty cycle 2% *2. when the device is mounted on 1in 2 copper pad of fr-4 board; 270 c/w when mounted on minimum copper pad. *3. human body model, 1.5k in series with 100pf electrical characteristics (ta=25 c) symbol min. typ. max. unit test conditions bv dss* 60 - - v v gs =0, i d =250 a bv dss / tj - 0.05 - v/ reference to 25 , i d =1ma v gs(th) 1 - 2.5 v v ds =v gs , i d =250 a i gss - - 10 a v gs =20v, v ds =0 - - 1 v ds =60v, v gs =0 i dss - - 100 a v ds =48v, v gs =0, tj=70 - 1.6 2 i d =200ma, v gs =4.5v - 1.23 5 i d =100ma, v gs =10v r ds(on)* - 1.26 4 i d =500ma, v gs =10v v sd - - 1.2 v i s =1.2a, v gs =0v g fs - 600 - ms v ds =10v, i d =600ma c iss - 62 80 c oss - 17.6 - c rss - 9 - pf v ds =25v, v gs =0, f=1mhz qg - 1 - qgs - 0.5 - qgd - 0.5 - nc i d =600ma, v ds =50v, v gs =4.5v t d(on) - 12 - t r - 10 - t d(off) - 56 - t f - 29 - ns v ds =30v, i d =600ma, r g =3.3 , v gs =10v, r d =52 *pulse test : pulse width 300 s, duty cycle 2%
cystech electronics corp. spec. no. : c403n3 issued date : 2006.05.22 revised date :2011.12.13 page no. : 3/7 MTNK2N3 cystek product specification typical characteristics typical output characteristics 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0123 4 typical output characteristics 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 01234 drain-source voltage---vds(v) drain current --- id(a) drain-source voltage ---vds(v) drain current --- id(a) vgs=3v 6v ta=125c ta=25c 10v 3.5v 4.0v 4.5v vgs=3v 10v 6v 3.5v 4.5v 4.0v typical transfer characteristics 0 100 200 300 400 500 600 700 800 900 1000 0123456 gate-source voltage---vgs(v) drain current ---id(a) vds=5v breakdown voltage variation with temperature 0.98 1 1.02 1.04 1.06 1.08 0 25 50 75 100 125 150 junction temperature---tj(c) normalized drain-source breakdown voltage static drain-source on-state resistance vs drain current 1 2 0.001 0.01 0.1 1 drain current-id(a) static drain-source on-state resistance- rds(on)() vgs=5v vgs=10v ta=25c static drain-source on-state resistance vs drain current 1 2 3 0.001 0.01 0.1 1 drain current-id(a) static drain-source on-state resistance- rds(on)() vgs=5v vgs=10v ta=125c
cystech electronics corp. spec. no. : c403n3 issued date : 2006.05.22 revised date :2011.12.13 page no. : 4/7 MTNK2N3 cystek product specification characteristic curves(cont.) static drain-source on-state resistance vs gate-source voltage 0 1 2 3 4 5 024681 0 static drain-source on-state resistance vs gate-source voltage 0 1 2 3 4 5 024681 gate-source voltage-vgs(v) static drain-source on-state resistance-rds(on)() gate-source voltage-vgs(v) static drain-source on-state resistance-rds(on)() ta=25c id=300ma id=50ma 0 id=300ma id=50ma ta=125c reverse drain current vs source-drain voltage 0 0.2 0.4 0.6 0.8 1 1.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 reverse drain current -idr(a) source-drain voltage-vsd(v) ta=125c ta=25c capacitance vs drain-to-source voltage 1 10 100 0 5 10 15 20 25 30 drain-source voltage -vds(v) capacitance---(pf) c oss ciss crss safe operating area 1 10 100 1000 11 0 drain-source voltage---vds(v) drain current---id(ma) 1 0 0 100s 1ms 10ms 100ms 1s dc operation in this area is limited by vgs=10v, single pulse, ta=25c
cystech electronics corp. spec. no. : c403n3 issued date : 2006.05.22 revised date :2011.12.13 page no. : 5/7 MTNK2N3 cystek product specification reel dimension carrier tape dimension
cystech electronics corp. spec. no. : c403n3 issued date : 2006.05.22 revised date :2011.12.13 page no. : 6/7 MTNK2N3 cystek product specification recommended wave soldering condition product peak temperature soldering time pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3 c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds time maintained above: ? temperature (t l ) 183 c 60-150 seconds 217 c 60-150 seconds ? time (t l ) peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 20-40 seconds ramp down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of t he package, measured on the package body surface.
cystech electronics corp. spec. no. : c403n3 issued date : 2006.05.22 revised date :2011.12.13 page no. : 7/7 MTNK2N3 cystek product specification sot-23 dimension *: typical inches millimeters inches millimeters dim min. max. min. max. dim min. max. min. max. h j k d a l g v c b 3 2 1 s style: pin 1.gate 2.source 3.drain marking: te 3-lead sot-23 plastic surface mounted package cystek package code: n3 702 device code a 0.1102 0.1204 2.80 3.04 j 0.0034 0.0070 0.085 0.177 b 0.0472 0.0630 1.20 1.60 k 0.0128 0.0266 0.32 0.67 c 0.0335 0.0512 0.89 1.30 l 0.0335 0.0453 0.85 1.15 d 0.0118 0.0197 0.30 0.50 s 0.0830 0.1083 2.10 2.75 g 0.0669 0.0910 1.70 2.30 v 0.0098 0.0256 0.25 0.65 h 0.0005 0.0040 0.013 0.10 notes: 1.controlling dimension: millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing specification or packing method, please c ontact your local cystek sales office. material: ? lead: pure tin plated ? mold compound: epoxy resin family, flammability solid burning class: ul94v-0 important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitable for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance .
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